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ltm4608a 1 4608afd typical a pplica t ion fea t ures a pplica t ions descrip t ion low v in , 8a dc/dc module regulator with tracking, margining, and frequency synchronization the ltm ? 4608a is a complete 8a switch mode dc/dc power supply with 1.75% total output voltage error. in- cluded in the package are the switching controller, power fets, inductor and all support components. operating over an input voltage range of 2.7v to 5.5v, the ltm4608a supports an output voltage range of 0.6v to 5v, set by a single external resistor. this high efficiency design delivers up to 8a continuous current (10a peak). only bulk input and output capacitors are needed to complete the design. the low profile package (2.82mm) enables utilization of unused space on the back side of pc boards for high density point-of-load regulation. the 0.630mm lga pads with 1.27mm pitch simplify pcb layout by providing stan- dard trace routing and via placement. the high switching frequency and current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. the device supports frequency syn - chronization, programmable multiphase and/or spread spectrum operation, output voltage tracking for supply rail sequencing and voltage margining. fault protection features include overvoltage protection, overcurrent protection and thermal shutdown. the power module is offered in a compact and thermally enhanced 9mm 15mm 2.82mm surface mount lga package. the ltm4608a is rohs compliant with pb-free finish. 2.7v to 5.5v input to 1.8v output dc/dc module ? regulator n complete standalone power supply n 1.75% total dc output error (C55c to 125c) n 2.7v to 5.5v input voltage range n 8a dc, 10a peak output current n 0.6v up to 5v output n output voltage tracking and margining n power good tracks margining n multiphase operation n parallel current sharing n onboard frequency synchronization n spread spectrum frequency modulation n overcurrent/thermal shutdown protection n current mode control/fast transient response n selectable burst mode ? operation n up to 95% efficiency n output overvoltage protection n small, low profile 9mm 15mm 2.82mm lga package (0.630mm pads) n telecom, networking and industrial equipment n storage systems n point of load regulation efficiency vs load current l , lt, ltc, ltm, linear technology, the linear logo, burst mode, module and polyphase are registered trademarks and ltpowercad is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. load current (a) 0 70 efficiency (%) 75 80 85 90 95 100 2 4 6 8 4608a ta01b 10 v out = 1.8v v in = 5v v in = 3.3v v in sv in sw run plllpf track v out fb i th i thm pgood mgn clkout gnd clkin clkin 4.87k 4608a ta01a 100f 10f pgood v out 1.8v v in 2.7v to 5.5v ltm4608a sgnd
ltm4608a 2 4608afd p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , sv in ...................................................... C0 .3v to 6v clkout ....................................................... C 0.3v to 2v pgood, plllpf, clkin, phmode, mode . C 0.3v to v in i th , i thm , run, fb, track,mgn, bsel ...... C0 .3v to v in v out , sw ...................................... C0 .3v to (v in + 0.3v) internal operating temperature range (note 2) .................................................. C 55c to 125c storage temperature range .................. C 55c to 125c (note 1) o r d er i n f or m a t ion e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in(dc) input dc voltage l 2.7 5.5 v v out(dc) output voltage, total variation with line and load c in = 10f 1, c out = 100f ceramic, 100f poscap, r fb = 6.65k, mode = 0v v in = 2.7v to 5.5v, i out = i out(dc)min to i out(dc)max (note 3) l 1.472 1.464 1.49 1.49 1.508 1.516 v v input specifications v in(uvlo) undervoltage lockout threshold sv in rising sv in falling 2.05 1.85 2.2 2.0 2.35 2.15 v v the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 5v unless otherwise noted. see figure 1. lead free finish tray part marking* package description temperature range (note 2) ltm4608aev#pbf ltm4608aev#pbf ltm4608av 68-lead (15mm 9mm 2.82mm) lga C40c to 125c ltm4608aiv#pbf ltm4608aiv#pbf ltm4608av 68-lead (15mm 9mm 2.82mm) lga C40c to 125c ltm4608ampv#pbf ltm4608ampv#pbf ltm4608ampv 68-lead (15mm 9mm 2.82mm) lga C55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ 1 2 3 4 5 6 7 8 9 10 11 lga package 68-lead (15mm 9mm 2.82mm) a gnd sw fb gnd run sgnd b c d e f g gnd v out v in top view clkout plllpf clkin sv in phmode mode bsel mgn pgood i thm track i th t jmax = 125c, ja = 25c/w, jcbottom = 7c/w, jctop = 50c/w, weight = 1.0g
ltm4608a 3 4608afd e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 5v unless otherwise noted. see figure 1. symbol parameter conditions min typ max units i q(vin) input supply bias current v in = 3.3v, no switching, mode = v in v in = 3.3v, no switching, mode = 0v v in = 3.3v, v out = 1.5v, switching continuous 400 1.15 55 a ma ma v in = 5v, no switching, mode = v in v in = 5v, no switching, mode = 0v v in = 5v, v out = 1.5v, switching continuous 450 1.3 75 a ma ma shutdown, run = 0, v in = 5v 1 a i s(vin) input supply current v in = 3.3v, v out = 1.5v, i out = 8a v in = 5v, v out = 1.5v, i out = 8a 4.5 2.93 a a output specifications i out(dc) output continuous current range (note 3) v out = 1.5v v in = 3.3v, 5.5v v in = 2.7v 0 0 8 5 a a ?v out(line) v out line regulation accuracy v out = 1.5v, v in from 2.7v to 5.5v, i out = 0a l 0.1 0.25 %/v ?v out(load) v out load regulation accuracy v out = 1.5v (note 3) v in = 3.3v, 5.5v, i load = 0a to 8a v in = 2.7v, i load = 0a to 5a l l 0.3 0.3 0.75 0.75 % % v out(ac) output ripple voltage i out = 0a, c out = 100f x5r ceramic, v in = 5v, v out = 1.5v 10 mv p-p f s switching frequency i out = 8a, v in = 5v, v out = 1.5v 1.25 1.5 1.75 mhz f sync sync capture range 0.75 2.25 mhz ?v out(start) turn-on overshoot c out = 100f, v out = 1.5v, i out = 0a v in = 3.3v v in = 5v 10 10 mv mv t start turn-on time c out = 100f, v out = 1.5v, v in = 5v, i out = 1a resistive load, track = v in , 100 s ?v out(ls) peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 100f ceramic, 100f poscap, v in = 5v, v out = 1.5v 15 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, v in = 5v, v out = 1.5v, c out = 100f 10 s i out(pk) output current limit c out = 100f v in = 2.7v, v out = 1.5v v in = 3.3v, v out = 1.5v v in = 5v, v out = 1.5v 8 11 13 a a a control section v fb voltage at fb pin i out = 0a, v out = 1.5v, v in = 2.7v to 5.5v l 0.590 0.587 0.596 0.596 0.602 0.606 v v ss delay internal soft-start delay 90 s i fb 0.2 a v run run pin on/off threshold run rising run falling 1.4 1.3 1.55 1.4 1.7 1.5 v v
ltm4608a 4 4608afd e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 5v unless otherwise noted. see figure 1. symbol parameter conditions min typ max units track tracking threshold (rising) tracking threshold (falling) tracking disable threshold run = v in run = 0v 0.57 0.18 v in C 0.5 v v v r fbhi resistor between v out and fb pins 9.95 10 10.05 k ?v pgood pgood range 10 % %margining output voltage margining percentage mgn = v in , bsel = 0v mgn = v in , bsel = v in mgn = v in , bsel = float mgn = 0v, bsel = 0v mgn = 0v, bsel = v in mgn = 0v, bsel = float 4 9 14 C4 C9 C14 5 10 15 C5 C10 C15 6 11 16 C6 C11 C16 % % % % % % note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4608a is tested under pulsed load conditions such that t j t a . the ltm4608ae is guaranteed to meet specifications from 0c to 125c internal temperature. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4608ai is guaranteed over the C40c to 125c internal operating temperature range and the ltm4608amp is tested and guaranteed over the full C55c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: see output current derating curves for different v in , v out and t a .
ltm4608a 5 4608afd v in (v) 2 v out (v) 1.5 2.0 2.5 3 5 4608a g06 1.0 0.5 0 4 3.0 3.5 4.0 6 i out = 6a v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v in (v) 2 v out (v) 1.5 2.0 2.5 3 5 4608a g05 1.0 0.5 0 4 3.0 3.5 4.0 6 i out = 8a v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v typical p er f or m ance c harac t eris t ics efficiency vs load current burst mode efficiency with 5v input v in to v out step-down ratio supply current vs v in load transient response load transient response efficiency vs load current efficiency vs load current load current 0 70 efficiency (%) 75 80 85 90 95 100 2 4 6 8 4608a g01 5v in 1.2v out 5v in 1.5v out 5v in 1.8v out 5v in 2.5v out 5v in 3.3v out continuous mode load current 0 70 efficiency (%) 75 80 85 90 95 100 2 4 6 8 4608a g02 3.3v in 1.2v out 3.3v in 1.5v out 3.3v in 1.8v out 3.3v in 2.5v out continuous mode load current (a) 0 efficiency (%) 90 95 100 2 4 5 4608a g03 80 70 85 75 1 3 6 7 2.7v in 1.0v out 2.7v in 1.5v out 2.7v in 1.8v out continuous mode v in to v out step-down ratio load current (a) 40 efficiency (%) 60 80 100 50 70 90 0.2 0.4 0.6 0.8 4608a g04 1.11.0 0.10 0.3 0.5 0.7 0.9 v out = 1.5v v out = 2.5v v out = 3.3v input voltage (v) 2.5 supply current (ma) 4.5 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 4608a g07 3.53 5 4 5.5 v o = 1.2v pulse-skipping mode v o = 1.2v burst mode i load 1a/div v in 2v/div v out 20mv/div ac coupled 20s/div v in = 5v v out = 3.3v, r fb = 2.21k 2a/s step c out = 100f x5r c1 = 100pf, c3 = 22pf from figure 18 4608a g08 20s/div v in = 5v v out = 2.5v, r fb = 3.09k 2.5a/s step c out = 100f x5r c1 = 120pf, c3 = 47pf from figure 18 4608a g09 i load 2a/div v out 20mv/div ac coupled
ltm4608a 6 4608afd temperature (c) ?55 v fb (mv) 592 594 596 35 95 4608a g14 590 ?25 5 65 598 600 602 125 v in = 5.5v v in = 3.3v v in = 2.7v load transient response start-up v fb vs temperature load regulation vs current 2.5v output current short-circuit protection (2.5v short, no load) load transient response load transient response v out 0.5v/div v in 2v/div 50s/div v in = 5v v out = 1.5v c out = 100f no load and 8a load (default 100s soft-start) 4608a g13 load current (a) 0 ?0.5 load regulation (%) ?0.4 0 ?0.2 ?0.3 ?0.6 2 4 ?0.1 6 8 4608a g15 fc mode v in = 3.3v v out = 1.5v short-circuit protection (2.5v short, 4a load) output current (a) 0 0 output voltage (v) 0.5 1.0 1.5 2.0 2.5 3.0 5 10 15 20 4608a g16 2v/div 2v/div 5a/div 50s/div 4608a g17 v out v in i out v in = 5v v out = 2.5v 5v/div 5v/div 5a/div 50s/div 4608a g18 v out v in i out load v in = 5v v out = 2.5v typical p er f or m ance c harac t eris t ics 20s/div v in = 5v v out = 1.8v, r fb = 4.87k 2.5a/s step c out = 100f x5r c1 = none, c3 = none from figure 18 4608a g10 i load 2a/div v out 20mv/div ac coupled 20s/div v in = 5v v out = 1.5v, r fb = 6.65k 2.5a/s step c out = 100f x5r c1 = none, c3 = none from figure 18 4608a g11 i load 2a/div v out 20mv/div ac coupled 20s/div v in = 5v v out = 1.2v, r fb = 10k 2.5a/s step c out = 2 100f c1 = 100pf, c3 = none from figure 18 4608a g12 i load 2a/div v out 20mv/div ac coupled
ltm4608a 7 4608afd plllpf (e3): phase locked loop lowpass filter. an in- ternal lowpass filter is tied to this pin. in spread spectrum mode, placing a capacitor here to sgnd controls the slew rate from one frequency to the next. alternatively, floating this pin allows normal running frequency at 1.5mhz, tying this pin to sv in forces the part to run at 1.33 times its normal frequency (2mhz), tying it to ground forces the frequency to run at 0.67 times its normal frequency (1mhz). phmode (b4): phase selector input. this pin determines the phase relationship between the internal oscillator and clkout. tie it high for 2-phase operation, tie it low for 3-phase operation, and float or tie it to v in /2 for 4-phase operation. mgn (b8): margining pin. increases or decreases the output voltage by the amount specified by the bsel pin. to disable margining, tie the mgn pin to a voltage divider with 50k resistors from v in to ground. see the applications information section and figure 20. bsel (b7): margining bit select pin. tying bsel low se- lects 5%, tying it high selects 10%. floating it or tying it to v in /2 selects 15%. track (e5): output voltage tracking pin. voltage track- ing is enabled when the track voltage is below 0.57v. if tracking is not desired, then connect the track pin to sv in . if track is not tied to sv in , then the track pins voltage needs to be below 0.18v before the chip shuts down even though run is already low. do not float this pin. a resistor divider and capacitor can be applied to the track pin to increase the soft-start time of the regulator. see the applications information section. can tie together for parallel operation and tracking. load current needs to be present during track down. p in func t ions v in (c1, c8, c9, d1, d3-d5, d7-d9 and e8): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. v out (c10-c11, d10-d11, e9-e11, f9-f11, g9-g11): power output pins. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. see table 1. gnd (a1-a11, b1, b9-b11, f3, f7-f8, g1-g8): power ground pins for both input and output returns. sv in (f4): signal input voltage. this pin is internally con- nected to v in through a lowpass filter. sgnd (e1): signal ground pin. return ground path for all analog and low power circuitry. tie a single connection to gnd in the application. mode (b5): mode select input. tying this pin high enables burst mode operation. tying this pin low enables forced continuous operation. floating this pin or tying it to v in /2 enables pulse-skipping operation. clkin (b3): external synchronization input to phase detector. this pin is internally terminated to sgnd with a 50k resistor. the phase locked loop will force the internal top power pmos turn on to be synchronized with the rising edge of the clkin signal. connect this pin to sv in to enable spread spectrum modulation. during external synchronization, make sure the plllpf pin is not tied to v in or gnd.
ltm4608a 8 4608afd fb (e7): the negative input of the error amplifier. internally, this pin is connected to v out with a 10k precision resistor. different output voltages can be programmed with an ad - ditional resistor between fb and gnd pins. in polyphase ? operation, tie fb pins together for parallel operation. see the applications information section for details. i th (f6): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. tie together in parallel operation. i thm (f5): negative input to the internal i th differential amplifier. tie this pin to sgnd for single phase operation. for polyphase operation, tie the masters i thm to sgnd while connecting all of the i thm pins together. pgood (c7): output voltage power good indicator. open-drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point. disabled during margining. run (f1): run control pin. a voltage above 1.5v will turn on the module. sw (c3-c5): switching node of the circuit is used for testing purposes. this can be connected to an electri - cally open circuit copper pad on the board for improved thermal performance. clkout (f2): output clock signal for polyphase opera- tion. the phase of clkout is determined by the state of the phmode pin. p in func t ions
ltm4608a 9 4608afd s i m pli f ie d b lock diagra m internal filter power control internal comp internal filter sv in track mgn bsel pgood mode run clkin clkout phmode plllpf sgnd i th i thm m1 22f c out 10f 10f 10f c in v in 2.7 to 5.5v v out 1.5v v out v in sw gnd fb 22pf 10k r fb 6.65k 4608a bd 0.22h m2 + symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 2.7v to 5.5v, v out = 1.5v) i out = 8a 10 f c out external output capacitor requirement (v in = 2.7v to 5.5v, v out = 1.5v) i out = 8a 100 f table 1. decoupling requirements. t a = 25c, block diagram configuration figure 1. simplified ltm4608a block diagram o pera t ion the ltm4608a is a standalone nonisolated switch mode dc/dc power supply. it can deliver up to 8a of dc output current with few external input and output capacitors. this module provides precisely regulated output voltage programmable via one external resistor from 0.6v dc to 5.0v dc over a 2.7v to 5.5v input voltage. the typical application schematic is shown in figure 18. the ltm4608a has an integrated constant frequency cur - rent mode regulator and built-in power mosfet devices with fast switching speed. the typical switching frequency is 1.5mhz. for switching noise sensitive applications, it can be externally synchronized from 0.75mhz to 2.25mhz. even spread spectrum switching can be implemented in the design to reduce noise.
ltm4608a 10 4608afd o pera t ion with current mode control and internal feedback loop compensation, the ltm4608a module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit and thermal shutdown in an overcurrent condition. internal overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. pulling the run pin below 1.3v forces the controller into its shutdown state, by turning off both m1 and m2 at low load current. the track pin is used for programming the output voltage ramp and voltage tracking during start-up. see applications information. the ltm4608a is internally compensated to be stable over all operating conditions. table 3 provides a guideline for input and output capacitances for several operating the typical ltm4608a application circuit is shown in figure 18. external component selection is primarily determined by the maximum load current and output voltage. refer to table 3 for specific external capacitor requirements for a particular application. v in to v out step-down ratios there are restrictions in the maximum v in to v out step- down ratio that can be achieved for a given input voltage. the ltm4608a is 100% duty cycle, but the v in to v out minimum dropout is a function of its load current. please refer to the curves in the typical performance charac - teristics section of this data sheet for more information. output voltage programming the pwm controller has an internal 0.596v reference voltage. as shown in the block diagram, a 10k 0.5% internal feedback resistor connects v out and fb pins together. the output voltage will default to 0.596v with conditions. the linear technology module power design tool is provided for transient and stability analysis. the fb pin is used to program the output voltage with a single external resistor to ground. multiphase operation can be easily employed with the synchronization and phase mode controls. up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the phmode pin to different levels. the ltm4608a has clock in and clock out for poly phasing multiple devices or frequency synchronization. high efficiency at light loads can be accomplished with selectable burst mode operation using the mode pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load operation in the typical performance characteristics. output voltage margining is supported, and can be pro- gramed from 5% to 15% using the mgn and bsel pins. the pgood pin is disabled during margining a pplica t ions i n f or m a t ion no feedback resistor. adding a resistor r fb from fb pin to gnd programs the output voltage: v out = 0.596v ? 10k + r fb r fb table 2. r fb resistor vs output voltage v out 0.596v 1.2v 1.5v 1.8v 2.5v 3.3v r fb open 10k 6.65k 4.87k 3.09k 2.21k input capacitors the ltm4608a module should be connected to a low ac impedance dc source. three 10f ceramic capacitors are included inside the module. additional input capaci- tors are only needed if a large load step is required up to the 4a level. a 47f to 100f surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long in - ductive leads, traces or not enough source capacitance.
ltm4608a 11 4608afd a pplica t ions i n f or m a t ion if low impedance power planes are used, then this 47f capacitor is not needed. for a buck converter, the switching duty-cycle can be estimated as: d = v out v in without considering the inductor current ripple, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1C d ( ) in the above equation, % is the estimated efficiency of the power module. the bulk capacitor can be a switcher- rated electrolytic aluminum capacitor, polymer capacitor for bulk input capacitance due to high inductance traces or leads. if a low inductance plane is used to power the device, then only one 10f ceramic is required. the three internal 10f ceramics are typically rated for 2a of rms ripple current, so the ripple current at the worse case for 8a maximum current is 4a or less. output capacitors the ltm4608a is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require - ments. c out can be a low esr tantalum capacitor, a low esr polymer capacitor or ceramic capacitor. the typical output capacitance range is from 47f to 220f. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is desired. table 3 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 3 matrix, and the linear technology ltpowercad? design tool is available for stability analysis. multiphase operation will reduce effective output ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple cur - rent cancellation, but the output capacitance will be more a function of stability and transient response. the linear technology ltpowercad design tool will calculate the output ripple reduction as the number phases implemented increases by n times. burst mode operation the ltm4608a is capable of burst mode operation in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for applications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. to enable burst mode operation, simply tie the mode pin to v in . during this operation, the peak current of the inductor is set to approximately 20% of the maximum peak current value in normal operation even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductors average current is greater than the load requirement. as the i th voltage drops below 0.2v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450a. the load current is now being supplied from the output capacitor. when the output voltage drops, causing i th to rise above 0.25v, the internal sleep line goes low, and the ltm4608a re - sumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation in applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. pulse-skipping operation allows the ltm4608a to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. floating the mode pin or tying it to v in /2 enables pulse-skipping operation. this allows discontinuous conduction mode (dcm) opera- tion down to near the limit defined by the chips minimum on-time (about 100ns). below this output current level, the converter will begin to skip cycles in order to maintain output regulation. increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency pwm.
ltm4608a 12 4608afd forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode pin to gnd. in this mode, inductor cur - rent is allowed to reverse during low output loads, the i th voltage is in control of the current comparator threshold table 3. output voltage response versus component matrix (refer to figure 18) 0a to 3a load step typical measured values c out1 vendors value part number c out2 vendors value part number tdk 22f, 6.3v c3216x7s0j226m sanyo poscap 150f, 10v 10tpd150m murata 22f, 16v grm31cr61c226ke15l c in (bulk) vendors value part number tdk 100f, 6.3v c4532x5r0j107mz sanyo 100f, 10v 10ce100fh murata 100f, 6.3v grm32er60j107m v out (v) c in (ceramic) c in (bulk)* c out1 (ceramic) c out2 (bulk) i th c1 c3 v in (v) droop (mv) peak-to- peak deviation (mv) recovery time (s) load step (a/s) r fb (k) 1.0 10f 100f 100f 2 none 68pf none 5 13 26 7 3 14.7 1.0 10f 100f 22f 1 150f 2 none none 100pf 5 17 34 8 3 14.7 1.0 10f 100f 100f 2 none 68pf none 3.3 13 26 7 3 14.7 1.0 10f 100f 22f 1 150f 2 none none 100pf 3.3 17 34 10 3 14.7 1.0 10f 100f 100f 2 none 68pf none 2.7 13 26 7 3 14.7 1.0 10f 100f 22f 1 150f 2 none none 100pf 2.7 17 34 8 3 14.7 1.2 10f 100f 100f 2 none 100pf none 5 16 32 8 3 10 1.2 10f 100f 22f 1 150f 2 none none 100pf 5 20 41 10 3 10 1.2 10f 100f 100f 2 none 100pf none 3.3 16 32 8 3 10 1.2 10f 100f 22f 1 150f 2 none none 100pf 3.3 20 41 10 3 10 1.2 10f 100f 100f 2 none 100pf none 2.7 16 32 10 3 10 1.2 10f 100f 22f 1 150f 2 none 47pf none 2.7 16 32 8 3 10 1.5 10f 100f 100f 2 none 100pf none 5 18 36 8 3 6.65 1.5 10f 100f 22f 1 150f 2 none none 47pf 5 20 41 12 3 6.65 1.5 10f 100f 100f 2 none 100pf none 3.3 16 32 10 3 6.65 1.5 10f 100f 22f 1 150f 2 none none 47pf 3.3 20 41 12 3 6.65 1.5 10f 100f 100f 2 none 100pf none 2.7 18 36 10 3 6.65 1.5 10f 100f 22f 1 150f 2 none none none 2.7 20 41 12 3 6.65 1.8 10f 100f 100f 1 none 47pf none 5 22 42 8 3 4.87 1.8 10f 100f 22f 1 150f 2 none none 47pf 5 21 42 12 3 4.87 1.8 10f 100f 100f 2 none 120pf none 3.3 21 43 12 3 4.87 1.8 10f 100f 22f 1 150f 2 none none 47pf 3.3 21 41 12 3 4.87 1.8 10f 100f 100f 2 none 120pf none 2.7 22 44 12 3 4.87 1.8 10f 100f 22f 1 150f 2 none none none 2.7 21 42 14 3 4.87 2.5 10f 100f 100f 1 none 100pf none 5 28 42 10 3 3.09 2.5 10f 100f 22f 1 150f 1 none 22pf none 5 33 60 10 3 3.09 2.5 10f 100f 100f 1 none 100pf none 3.3 30 60 10 3 3.09 2.5 10f 100f 22f 1 150f 1 none 22pf none 3.3 21 41 10 3 3.09 3.3 10f 100f 100f 1 100pf 22pf none 5 38 74 10 3 2.21 3.3 10f 100f 22f 1 150f 1 none none none 5 39 75 12 3 2.21 *bulk capacitance is optional if v in has very low input impedance. a pplica t ions i n f or m a t ion throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from revers- ing until the ltm4608as output voltage is in regulation. multiphase operation for output loads that demand more than 8a of current, multiple ltm4608as can be cascaded to run out of phase to
ltm4608a 13 4608afd a pplica t ions i n f or m a t ion provide more output current without increasing input and output voltage ripple. the clkin pin allows the ltm4608a to synchronize to an external clock (between 0.75mhz and 2.25mhz) and the internal phase locked loop allows the ltm4608a to lock onto clkins phase as well. the clkout signal can be connected to the clkin pin of the following ltm4608a stage to line up both the frequency and the phase of the entire system. tying the phmode pin to sv in , sgnd or sv in /2 (floating) generates a phase difference (between clkin and clkout) of 180, 120 or 90 respectively, which corresponds to a 2-phase, 3-phase or 4-phase operation. a total of 6 phases can be cascaded to run simultaneously with respect to each other by programming the phmode pin of each ltm4608a to different levels. for a 6-phase example in figure 2, the 2nd stage that is 120 out of phase from the 1st stage can generate a 240 (phmode = 0) clkout signal for the 3rd stage, which then can generate a clkout signal thats 420, or 60 (phmode = sv in ) for the 4th stage. with the 60 clkin input, the next two stages can shift 120 (phmode = 0) for each to generate a 300 signal for the 6th stage. finally, the signal with a 60 phase shift on the 6th stage (phmode is floating) goes back to the 1st stage. figure 3 shows the configuration for 12-phase operation. a multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used. figure 2. 6-phase operation figure 3. 12-phase operation 4608a f02 0 +120 phase 1 clkout clkin phmode 120 phase 3 clkout clkin phmode 240 +180 +120 phase 5 clkout clkin phmode s vin (420) 60 phase 2 clkout clkin phmode +120 180 phase 4 clkout clkin phmode +120 300 phase 6 clkout clkin phmode 4608 f02 0 +120 phase 1 clkout clkin phmode 120 phase 5 clkout clkin phmode 240 +180 +120 phase 9 clkout clkin phmode s vin (420) 60 phase 3 clkout clkin phmode +120 180 phase 7 clkout clkin phmode +120 300 phase 11 clkout clkin phmode 4608a f03 90 +120 phase 4 clkout clkin phmode out1 out2 v + ltc6908-2 210 phase 8 clkout clkin phmode 330 +180 +120 phase 12 clkout clkin phmode s vin (510) 150 phase 6 clkout clkin phmode +120 270 phase 10 clkout clkin phmode +120 (390) 30 phase 2 clkout clkin phmode
ltm4608a 14 4608afd a pplica t ions i n f or m a t ion the ltm4608a device is an inherently current mode con - trolled device. parallel modules will have very good current sharing. this will balance the thermals on the design. tie the i th pins of each ltm4608a together to share the current evenly. to reduce ground potential noise, tie the i thm pins of all ltm4608as together and then connect to the sgnd at only one point. figure 19 shows a schematic of the parallel design. the fb pins of the parallel module are tied together. with parallel operation, input and out - put capacitors may be reduced in part according to the operating duty cycle. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can- cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure 4 shows this graph. spread spectrum operation switching regulators can be particularly troublesome where electromagnetic interference (emi) is concerned. switching regulators operate on a cycle-by-cycle basis to transfer power to an output. in most cases, the frequency of operation is fixed based on the output load. this method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics). to reduce this noise, the ltm4608a can run in spread spectrum operation by tying the clkin pin to sv in . in spread spectrum operation, the ltm4608as internal oscillator is designed to produce a clock pulse whose period is random on a cycle-by-cycle basis but fixed between 70% and 130% of the nominal frequency. this has the benefit of spreading the switching noise over a range of frequencies, thus significantly reducing the peak noise. spread spectrum operation is disabled if duty factor (v o /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4608a f04 rms input ripple current dc load current 6-phase 4-phase 3-phase 2-phase 1-phase figure 4. normalized input rms ripple current vs duty factor for one to six phases
ltm4608a 15 4608afd a pplica t ions i n f or m a t ion clkin is tied to ground or if its driven by an external frequency synchronization signal. a capacitor value of 0.01f must be placed from the plllpf pin to ground to control the slew rate of the spread spectrum frequency change. add a control ramp on the track pin with r sr and c sr referenced to v in . figure 21 shows an example for spread spectrum operation. r sr 1 ? ln 1 ? 0.592 v in ? ? ? ? ? ? ? 500 ? c sr ? ? ? ? ? ? output voltage tracking output voltage tracking can be programmed externally using the track pin. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the figure 5. dual outputs (3.3v and 1.5v) with tracking same as the slave regulators feedback divider to implement coincident tracking. the ltm4608a uses an accurate 10k resistor internally for the top feedback resistor. figure 5 shows an example of coincident tracking: slave = 1+ 10k r fb4 ? ? ? ? ? ? ? v track v track is the track ramp applied to the slaves track pin. v track has a control range of 0v to 0.596v, or the internal reference voltage. when the masters output is divided down with the same resistor values used to set the slaves output, this resistor divider is connected to the slaves track pin. the slave will then coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. voltage tracking is disabled when v track is more than 0.596v. v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin run track track r sr c sr c2 100pf c3 22pf r fb1 2.21k 100f master 3.3v 7a v in 5v tie to v in for disable and default 100s soft-start apply a control ramp with r sr and c sr tied to v in where t = ?(ln (1 ? 0.596/v in ) ? r sr ? c sr ) or apply an external tracking ramp ltm4608a sgnd v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin run master 3.3v r fb2 6.65k 50k 50k v in r fb3 10k r fb4 6.65k 4608a f05 c1 100f c4 100f slave 1.5v 8a ltm4608a sgnd +
ltm4608a 16 4608afd a pplica t ions i n f or m a t ion the track pin of the master can be controlled by an external ramp or by r sr and c sr in figure 5 referenced to v in . the rc ramp time can be programmed using equation: t = C ln 1C 0.596v v in ? ? ? ? ? ? ? r sr ? c sr ? ? ? ? ? ? ? ? ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the mas - ters track pin. as mentioned above, the track pin has a control range from 0v to 0.596v. the masters track pin slew rate is directly equal to the masters output slew rate in volts/time: mr sr ? 10k = r fb3 where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r fb3 is equal the 10k. r fb4 is derived from equation: r fb4 = 0.596v v fb 10k + v fb r fb2 C v track r fb3 where v fb is the feedback voltage reference of the regulator and v track is 0.596v. since r fb3 is equal to the 10k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r fb4 is equal to r fb2 with v fb = v track . therefore r fb3 = 10k and r fb4 = 6.65k in figure 5. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r fb3 can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. for example: mr = 3.3v/ms and sr = 1.5v/ms. then r fb3 = 22.1k. solve for r fb4 to equal to 4.87k. for applications that do not require tracking or sequencing, simply tie the track pin to sv in to let run control the turn on/off. connecting track to sv in also enables the ~100s of internal soft-start during start-up. load current needs to be present during track down. power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation. this pin monitors a 10% window around the regulation point. as shown in figure 20, the sequencing function can be realized in a dual output application by controlling the run pins and the pgood signals from each other. the 1.5v output begins its soft starting after the pgood signal of 3.3v output becomes high, and 3.3v output starts its shut down after the pgood signal of 1.5v output becomes low. this can be applied to systems that require voltage sequencing between the core and sub-power supplies. figure 6. output voltage coincident tracking output voltage (v) time master output slave output 4608a f06
ltm4608a 17 4608afd figure 7. 3.3v in , 2.5v and 1.5v out power loss figure 8. 5v in , 3.3v and 1.5v out power loss load current (a) 0 power loss (w) 2.0 2.5 3.0 8 4608a f07 1.5 1.0 0 2 4 6 0.5 4.0 3.5 3.3v in 1.5v out 3.3v in 2.5v out load current (a) 0 power loss (w) 2.0 2.5 3.0 8 4608a f08 1.5 1.0 0 2 4 6 0.5 4.0 3.5 5v in 1.5v out 5v in 3.3v out a pplica t ions i n f or m a t ion slope compensation the module has already been internally compensated for all output voltages. table 3 is provided for most applica - tion requirements. a spice model will be provided for other control loop optimization. for single module operation, connect i thm pin to sgnd. for parallel operation, tie i thm pins together and then connect to sgnd at one point. tie i th pins together to share currents evenly for all phases. output margining for a convenient system stress test on the ltm4608as output, the user can program the ltm4608as output to 5%, 10% or 15% of its normal operational voltage. the margin pin with a voltage divider is driven with a small three-state gate as shown in figure 18, for the three margin states (high, low, no margin). when the mgn pin is < 0.3v, it forces negative margining in which the output voltage is below the regulation point. when mgn is > v in C 0.3v, the output voltage is forced above the regulation point. the amount of output voltage margining is determined by the bsel pin. when bsel is low, it is 5%. when bsel is high, it is 10%. when bsel is floating, it is 15%. when margining is active, the internal output overvoltage and undervoltage comparators are disabled and pgood re - mains high. margining is disabled by tying the mgn pin to a voltage divider as shown in figure 20. thermal considerations and output current derating the power loss curves in figures 7 and 8 can be used in coordination with the load current derating curves in figures 9 to 16 for calculating an approximate ja for the module with various heat sinking methods. thermal models are derived from several temperature measurements at the bench, and thermal modeling analysis. thermal ap- plication note 103 provides a detailed explanation of the analysis for the thermal models and the derating curves. tables 4 and 5 provide a summary of the equivalent ja for the noted conditions. these equivalent ja parameters are correlated to the measured values and improve with air flow. the junction temperature is maintained at 125c or below for the derating curves.
ltm4608a 18 4608afd a pplica t ions i n f or m a t ion figure 9. no heat sink with 3.3v in to 1.5v out figure 10. bga heat sink with 3.3v in to 1.5v out figure 11. no heat sink with 5v in to 1.5v out figure 12. bga heat sink with 5v in to 1.5v out figure 13. no heat sink with 3.3v in to 2.5v out figure 14. bga heat sink with 3.3v in to 2.5v out ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f09 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f10 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f11 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f12 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f13 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f14 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm
ltm4608a 19 4608afd a pplica t ions i n f or m a t ion table 4. 1.5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 9, 11 3.3, 5 figures 7, 8 0 none 25 figures 9, 11 3.3, 5 figures 7, 8 200 none 21 figures 9, 11 3.3, 5 figures 7, 8 400 none 20 figures 10, 12 3.3, 5 figures 7, 8 0 bga heat sink 23.5 figures 10, 12 3.3, 5 figures 7, 8 200 bga heat sink 22 figures 10, 12 3.3, 5 figures 7, 8 400 bga heat sink 22 table 5. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figure 15 5 figure 8 0 none 25 figure 15 5 figure 8 200 none 21 figure 15 5 figure 8 400 none 20 figure 16 5 figure 8 0 bga heat sink 23.5 figure 16 5 figure 8 200 bga heat sink 22 figure 16 5 figure 8 400 bga heat sink 22 figure 15. no heat sink with 5v in to 3.3v out figure 16. bga heat sink with 5v in to 3.3v out ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f15 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm ambient temperature (c) 40 load current (a) 5 6 7 120 4608a f16 4 3 0 1 60 80 100 50 70 90 110 2 9 8 400lfm 200lfm 0lfm
ltm4608a 20 4608afd a pplica t ions i n f or m a t ion figure 17. recommended pcb layout safety considerations the ltm4608a modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. layout checklist/example the high integration of ltm4608a makes the pcb board layout very simple and easy. however, to optimize its electrical and thermal performance, some layout con - siderations are still necessary. ? use large pcb copper areas for high current path, including v in , gnd and v out . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci- tors next to the v in , gnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? t o minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on the pads, unless they are capped. ? use a separated sgnd ground copper area for com- ponents connected to signal pins. connect the sgnd to gnd underneath the unit. figure 17 gives a good example of the recommended layout. gnd gnd gnd 4608a f17 c in c out c out c out c in v in v out
ltm4608a 21 4608afd typical a pplica t ions figure 18. typical 3v to 5.5v in , 2.5v at 8a design figure 19. two ltm4608as in parallel, 1.5v at 16a design. see also dual 8a per channel ltm4616 v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin run track 100f 6.3v x5r c4 100pf 10f 3.32k v out 1.5v 16a v in 3v to 5.5v ltm4608a sgnd v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin c2 10f c3 100f 6.3v x5r c1 100f 6.3v x5r 4608a f19 ltm4608a sgnd 50k 50k v in v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn pgood (high = 10%) (float = 15%) (low = 5%) a in 2 u1: pericom pi74st1g126cex or toshiba tc7sz126afe 1 5 4 3 oe 100k v in v in y out bsel mode phmode clkout gnd clkin clkin c1 220pf c out 100f c in 10f c3 47pf r fb 3.09k 50k 50k 4608a f18 v out 2.5v 8a 8a at 5v input 6a at 3.3v input v in 3v to 5.5v ltm4608a sgnd u1 oe h h l a in h l x y out h l z mgn h l v in /2 margin value + of bsel selection ? of bsel selection no margin
ltm4608a 22 4608afd typical a pplica t ions figure 20. dual ltm4608a output sequencing application. see also dual 8a per channel ltm4616 figure 21. 2.7v to 5.5v in , 1.2v out design in spread spectrum operation v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin clkin 100f 6.3v x5r 100k 100k r fb1 2.21k 50k 50k r2 100k r1 100k c3 22pf v in r fb2 6.65k v out2 3.3v 7a v out1 1.5v 8a v in 5v d1 mmsd4148 d2 mmsd4148 ltm4608a sgnd v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin c2 100pf c1 100f 6.3v x5r c4 100f sanyo poscap 10m 4608a f20 ltm4608a sgnd shdn shdn shdn 3.3v 1.5v + v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn pgood bsel mode phmode clkout gnd clkin sv in c2 100f 6.3v x5r c1 100f 6.3v x5r 10f 100pf 10k 4608a f21 v out 1.2v/8a 5a at 2.7v input v in 2.7v to 5.5v ltm4608a sgnd r sr 180k c sr 0.22f 0.01f 50k 50k v in
ltm4608a 23 4608afd typical a pplica t ions figure 22. 4-phase, four outputs (3.3v, 2.5v, 1.8v and 1.5v) with tracking v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin clkin track or ramp control r10 2.21k 100f 6.3v x5r c2 100pf c4 22pf r1 4.87k c3 100f 6.3v x5r c8 100pf r2 3.09k c1 100f 6.3v x5r c7 220pf c8 47pf v out1 3.3v 7a v in 5v ltm4608a sgnd v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin 3.3v r4 10k r5 3.09k v out2 2.5v 8a ltm4608a sgnd v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin 3.3v r8 6.65k 4608a f22 r6 10k r7 6.65k c5 100f 6.3v x5r c9 100f 6.3v sanyo poscap 10m v out4 1.5v 8a ltm4608a sgnd v in sv in sw run plllpf track mode phmode v out fb i th i thm pgood bsel mgn clkout gnd clkin 3.3v r8 10k r9 4.87k v out3 1.8v 8a ltm4608a sgnd + 50k 50k v in
ltm4608a 24 4608afd p ackage descrip t ion lga package 68-lead (15mm 9mm 2.82mm) (reference ltc dwg # 05-08-1821 rev ?) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222 5. primary datum -z- is seating plane 6. the total number of pads: 68 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature 2.72 ? 2.92 detail b detail b substrate mold cap 0.290 ? 0.350 2.200 ? 2.600 // bbb z z package top view 9.00 bsc 15.00 bsc 4 pad ?a1? corner x y aaa z aaa z package bottom view 3 pads see notes detail a 0.630 0.025 sq. 68x s yxeee suggested pcb layout top view lga 68 1207 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a 7.620 bsc 1.27 bsc 12.70 bsc pad 1 fg e abcd 8 2 1 4 3 5 6 7 11 9 10 0.000 1.270 1.270 2.540 2.540 3.810 3.810 6.350 6.350 3.810 3.810 5.080 5.080 2.540 2.540 1.270 1.270 0.000 symbol aaa bbb eee tolerance 0.15 0.10 0.05 p ackage p ho t o
ltm4608a 25 4608afd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 12/10 voltage changed in the typical application drawing. changes made to the absolute maximum ratings section. updated the pin configuration package dimensions. changes made to the v out conditions in the electrical characteristics section. updated note 2 in the electrical characteristics section. replaced graphs g05 and g06 in the typical performance characteristics section. updated mgn (b8) in the pin functions section. text changes made to the applications information section. changes made to figures 5, 18, 20, 21, 23. updated the related parts table. 1 2 2 2 4 5 7 10, 11, 14, 19 15, 21, 22, 23 26 c 3/11 updated pin configuration drawing removed pin configuration drawing from pin functions added value of 0.22h to inductor in figure 1 updated figure 3 updated figure 17 added package photo 2 8 9 13 20 24 d 3/12 revised the typical application circuit. changed the format of the pin assignment table. 1 26 (revision history begins at rev b)
ltm4608a 26 4608afd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com ? linear technology corporation 2008 lt 0312 rev d ? printed in usa r ela t e d p ar t s part number description comments ltc2900 quad supply monitor with adjustable reset timer monitors four supplies, adjustable reset timer ltc2923 power supply tracking controller tracks both up and down, power supply sequencing ltm4616 low v in dual 8a dc/dc step-down module regulator 2.7v v in 5.5v, 0.6v v out 5v, 15mm 15mm 2.82mm lga ltm4628 dual 8a, 26v, dc/dc step-down module regulator 4.5v v in 26.5v, 0.6v v out 5.5v, remote sense amplifier, internal temperature sensing output, 15mm 15mm 4.32mm lga ltm4601/ ltm4601a 12a dc/dc module regulator with pll, output tracking/ margining and remote sensing synchronizable, polyphase operation, ltm4601-1/ltm4601a-1 version has no remote sensing, lga and bga package options, mp version available ltm4602 6a dc/dc module regulator pin compatible with the ltm4600, lga package ltm4618 6a dc/dc module regulator with pll and output tracking/margining and remote sensing synchronizable, polyphase operation ltm4604a low v in 4a dc/dc module regulator 2.375v v in 5.5v, 0.8v v out 5v, 9mm 15mm 2.32mm lga package LTM4605 5a to 12a buck-boost module regulator 4.5v v in 20v, 0.8v v out 16v, 15mm 15mm 2.82mm lga package ltm8020 high v in 0.2a dc/dc step-down module regulator 4v v in 36v, 1.25v v out 5v, 6.25mm 6.25mm 2.32mm lga package ltm8021 high v in 0.5a dc/dc step-down module regulator 3v v in 36v, 0.8v v out 5v, 6.25mm 11.25mm 2.82mm lga package ltm8022 high v in 1a dc/dc step-down module regulator 3.6v v in 36v, 0.8v v out 10v, 11.25mm 9mm 2.82mm lga package ltm8023 high v in 2a dc/dc step-down module regulator 3.6v v in 36v, 0.8v v out 10v, 11.25mm 9mm 2.82mm lga package p ackage descrip t ion pin assignment table (arranged by pin number) pin name pin function pin name pin function pin name pin function pin name pin function pin name pin function pin name pin function pin name pin function a1 gnd b1 gnd c1 v in d1 v in e1 sgnd f1 run g1 gnd a2 gnd b2 C c2 C d2 C e2 C f2 clkout g2 gnd a3 gnd b3 clkin c3 sw d3 v in e3 plllpf f3 gnd g3 gnd a4 gnd b4 phmode c4 sw d4 v in e4 C f4 sv in g4 gnd a5 gnd b5 mode c5 sw d5 v in e5 track f5 i thm g5 gnd a6 gnd b6 C c6 C d6 C e6 C f6 i th g6 gnd a7 gnd b7 bsel c7 pgood d7 v in e7 fb f7 gnd g7 gnd a8 gnd b8 mgn c8 v in d8 v in e8 v in f8 gnd g8 gnd a9 gnd b9 gnd c9 v in d9 v in e9 v out f9 v out g9 v out a10 gnd b10 gnd c10 v out d10 v out e10 v out f10 v out g10 v out a11 gnd b11 gnd c11 v out d11 v out e11 v out f11 v out g11 v out

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